Recently, in order to achieve mass production and lower production cost in production of semiconductor devices, it is desired to obtain as many semiconductor elements (semiconductor chips) as possible from a semiconductor substrate (semiconductor wafer). Thus, depending on the types and sizes of semiconductor elements, several thousand semiconductor elements or more are obtained from a semiconductor substrate.
On the other hand, according to reduction in size and weight of electronic devices in which the semiconductor devices are mounted, it is attempting to reduce thickness and weight of packages (cases) housing the semiconductor elements, and to narrow pitches of terminals. Thus, a bump connection method is proposed to connect a semiconductor element with a circuit board on which the semiconductor element is mounted, instead of a conventional wire connection method.
FIG. 12A depicts a state in which a plurality of semiconductor elements are formed in a surface of a semiconductor substrate. In FIG. 12A, a rectangle represents a semiconductor element 1A. Moreover, a cross section A-A′ of a semiconductor substrate 1 is depicted in 12B.
Namely, a plurality of bumps 3 are arranged through a multilayer wiring layer or rewiring layer 2 in each of the semiconductor element 1A formed in the surface of the semiconductor substrate 1.
Then, semiconductor elements 1A are individually subjected to an electric test so as to detect a non-defective or a defective before singulated from the semiconductor substrate 1, i.e., the semiconductor substrate 1 is diced and the semiconductor elements 1A are separated into single pieces.
As depicted in FIG. 12C, the electric test is performed in such a manner that a test probe 4 is brought into contact with the bump 3 which is a terminal for external connection in each of the semiconductor elements 1A. That is, as depicted in FIG. 12D, a plurality of the semiconductor elements 1A formed in an effective section (a section surrounded by a dashed line circle, ES) in the semiconductor substrate 1 are subjected to the electric test using a test device (not depicted) which is connected to the test probe, so as to detect a defective semiconductor element.
From a result of the detection, an existence state of defectives (generally, called as “map data”) is obtained. The existence state of defectives is represented by map information 21 as depicted in FIG. 12E. In the map data, a rectangle represents a semiconductor element, and a rectangle with “x” represents a defective semiconductor element.
As depicted in FIG. 12F, the semiconductor substrate 1, of which map information is obtained, is placed on a dicing tape 5, and then singulated into each of the semiconductor elements by a dicing method or the like using a dicing blade 6.
A cross section of the semiconductor substrate 1 which has been subjected to the dicing process is depicted in FIG. 12G.
Thereafter, as depicted in FIG. 12H, from a back surface of the dicing tape 5 (a surface on which the semiconductor substrate 1 is not placed), each of the semiconductor element 1A is pushed up by a push-up pin 7 and adsorbed to an adsorption collet 8, so as to be picked up. At this time, the defective semiconductor element is not picked up according to the map data. Then, the picked up non-defective (defect-free) semiconductor element 1A is sent to a next step, for example, while it is housed in a case (tray) for a semiconductor element (not depicted).
Meanwhile, it is not easy to efficiently pick up the non-defective (defect-free) semiconductor element according to the map data. In the semiconductor substrate 1, a layout is selected to form as many semiconductor elements 1A as possible in the largest section, from which the semiconductor elements 1A are obtained, in order to improve efficiency of picking up the semiconductor element 1A. In the semiconductor substrate which has been subjected to the dicing process, all the semiconductor elements 1A appear the same. Thus, location information of the non-defective semiconductor element in the map data may be precisely matched (overlapped) to location information of a great number of the semiconductor elements, so that the non-defective (defect-free) semiconductor elements are picked up from the semiconductor elements having similar appearances.
However, the semiconductor substrate 1 is not marked, and thus, it is difficult to precisely overlap the map data to the semiconductor substrate, which has been subjected to dicing. As one of methods for the precise overlapping, conventionally, a method for matching a distance datum from the center of a semiconductor substrate with a distance datum in map data has been proposed. However, in the case of this method, a problem occurs that a distance datum does not match with a distance in the semiconductor substrate 1 due to a shift error of an equipment used for sorting and acquiring the semiconductor element, and deformation of the dicing tape 5 caused by dicing the semiconductor substrate. Therefore, as a final solution, the alignment has been confirmed by visual inspection.
It is difficult to precisely operate the alignment by visual inspection, and a position of a first semiconductor element of the map data may be misplaced. As a result, there is a high possibility that the defective semiconductor element is falsely recognized. The false recognition of the defective semiconductor element is mostly detected by a test which is performed after a semiconductor device has been assembled. This causes unnecessary loss of a wiring substrate, on which the semiconductor element is mounted, etc., and delay in the production of the semiconductor devices and electronic devices.
Therefore, a method for avoiding the false recognition of the position of the first semiconductor element of the map data or a method for detecting the false recognition are desired. Consequently, a method is proposed that an ink mark is formed in a pellet which is present outside of an effective section in a semiconductor substrate, and a non-defective or defective determination test is performed by a coordinate system using the ink mark as a base point, thereby forming the ink mark in a detected defective (for example, Japanese Laid-open Patent Publication No. 2002-184819).
However, in the ink mark method, the ink mark is not formed on a small semiconductor element or a semiconductor element in which a bump is formed, and moreover the ink needs to be controlled. Moreover, in the case of a method, in which a non-defective (defective-free) semiconductor element is obtained by using map data, the method is only effective when the ink mark is formed on a semiconductor element in a semiconductor substrate according to test results. The method is not employed to a semiconductor substrate, on which a test without using the ink mark is performed.
On the other hand, a method is proposed that a semiconductor element having a certain circuit pattern which is different from a typical one is formed in a certain point of a semiconductor substrate, and the semiconductor element is detected by a test, and then map data is formed using the semiconductor element as a base point (for example, Japanese Laid-open Patent Publication No. 57-95644).
According to such method, a section for forming the semiconductor element having a certain circuit pattern which is different from a typical one is formed on the semiconductor substrate. Moreover, as the semiconductor element having a certain circuit pattern which is different from a typical one is different from other typical semiconductor elements, it is not used as a product. Furthermore, on a large semiconductor substrate, a photomask including a pattern of the semiconductor element having a certain circuit pattern which is different from a typical one and a pattern of a semiconductor element to be formed into a product is repeatedly applied on a semiconductor substrate, so as to produce a circuit pattern of the semiconductor element. Therefore, the semiconductor elements each having a certain circuit pattern which is different from that of the semiconductor element to be formed into a product are formed as many as shot numbers, causing decrease in a percentage of acquiring the semiconductor element to be formed into a product. In order to avoid the decrease of the percentage, a mask for the semiconductor element having a certain circuit pattern which is different from that of the semiconductor element to be formed into a product, and a mask for the product are provided, increasing of production cost.